The present invention relates to a novel plating method to be and particularly to a plating method used for forming wiring on a substrate in a semiconductor device, such as an LSI or the like.
Both an aluminum sputtering method and a tungsten CVD method have been used for depositing a metal film to be used as wiring in a semiconductor device. However, the wiring is expected to be made finer as a result of continuing progress in achieving higher integration of LSI devices, and, consequently, there arise problems caused by delay in signal transfer speed due to high resistivity and a decrease in reliability due to low migration resistance when a wiring material such as aluminum, tungsten or the like is used. Although copper is expected to be used as a wiring material in place of the conventional material because it is capable of realizing low resistivity and high electro-migration resistance, there are many problems to be solved if this wiring material is to be used.
In a case of using copper as the wiring material, it is generally difficult to use a dry etching method, which is used to form aluminum wiring, as the wiring forming method. Therefore, a method is employed in which an insulation film is formed on a substrate in advance, portions of the insulation film corresponding to locations of the wiring or inter-layer connecting conductive bodies are machined to produce a depressed shape, and then the depressed portions are filled with copper.
As a filling method, there is a method of selectively filling only the depressed portion, but a more common method is one in which the whole surface of the substrate, including the depressed portions, is metallized, and then chemical-mechanical polishing (CMP polishing) is performed on the surface to remove the surface layer. As the metallizing method for filling a depressed portions, there are dry metallizing methods, such as a sputtering method, a chemical vapor deposition method (CVD method) and the like, and wet metallizing methods, such as electroless plating, electrolytic plating and the like.
In recent years, much attention has been focused on a process combining the wet metallizing method and the CMP polishing, because the wet metallizing method is advantageous in that it has a good filling capability with respect to very small depressed portions for forming high density wiring. Japanese Patent Application Laid-Open No.8-83796 discloses a method of filling wiring trenches through electroless plating using silver, copper, gold, nickel, cobalt or palladium.
In order to achieve a reduction in the resistivity of wiring to a value lower than that of aluminum wiring, it is considered that only silver, copper and gold may be used. In a case of using such a metal, a palladium seed layer is formed by collimator sputtering, and then an electroless plating film is formed on the palladium seed layer. In such a method, the process of forming the palladium seed layer by collimator sputtering becomes a bottleneck, and, accordingly, it is impossible with this procedure to make the wiring sufficiently fine. In addition, palladium will easily react with the electroless metal to easily penetrate into the wiring metal, which causes an increase in the resistivity. This result is inconsistent with the objective of employing a low resistive metal for replacing aluminum.
Further, Japanese Patent Application Laid-Open No.6-29246 discloses a method in which a substance serving as a catalyst for electroless plating reaction is added to the inside of trenches and holes through wet treatment, and then the inside of the holes are filled with a metal by electroless plating. In this case, palladium is used for the catalyst. For purposes of reducing the resistivity of wiring to a value lower than that of aluminum wiring, electroless plating of copper is the best method. However, palladium easily reacts with copper to increase the resistivity, and consequently the essential object of reducing the resistivity can not be attained with this procedure.
Further, there is a well known method in which a zinc oxide layer is formed in a silicon oxide film (an insulator film) having very small depressed portions formed through spray pyrolysis, and palladium or the like is substitutively plated while the zinc oxide layer is being melted, and then a copper or gold film is formed by electrolytic plating or electroless plating using the palladium as a seed layer. However, since palladium is used in this method, similar to in the above-mentioned method, there is a problem in that the resistivity of the wiring metal is increased. In addition to this, there is a possibility that the mixing of zinc deteriorates the characteristic of the element.
Furthermore, Japanese Patent Application Laid-Open No.7-283219, Japanese Patent Application Laid-Open No.7-122556 and Japanese Patent Application Laid-Open No.8-83796 disclose methods in which a titanium film, a titanium nitride film and a tantalum film are successively formed on a surface of an insulator layer having depressed portions formed thereon, and then copper is electrolytically plated on the films to form wiring. In this case, in contrast to the aforementioned methods, it seems that no increase in resistivity of the copper wiring by a different kind of element, such as palladium, is caused. However, because the electric resistivity of the multilayer thin film of titanium, titanium nitride and tantalum is large, the method has a disadvantage in that the capability of filling the depressed portions is poor when the multilayer thin film is used as a cathode for electrolytic plating.
In electrolytic plating, the application of a uniform electric field is required in order to obtain a uniform deposition. However, in a case of a cathode having a high resistivity, as described above, it is difficult to apply the electric field to a portion near the bottom of the depressed portion. Particularly, it is anticipated that the filling capability is deteriorated as the depressed portion is narrowed and deepened (the aspect ratio is increased). This is a fatal weakness of this method for forming fine wiring.
Although various methods of filling depressed portions with a metal through use of a wet metallizing method, which is advantageous in filling very small depressed portions, have been studied, as described above, each of the methods has problems. Since the object is to reduce the resistivity of wiring to a value lower than that of aluminum wiring, alternative metallic materials are limited to copper, silver and gold.
However, since these metals likely react with a insulator layer or silicon, four surfaces of the metal wiring need to be protected by a barrier layer made of an electric conductor. Materials capable of functioning as a metallic barrier layer, are metal nitrides such as titanium nitride, tungsten nitride, tantalum nitride and so on, high melting point metals, such as tantalum, tungsten and so on, and alloys of the high melting point metals.
However, since the metal nitrides, the high melting point metals and the alloys of the high melting point metals are inactive to electroless plating reaction, it has been impossible to perform electroless plating directly on the metal nitride, the high melting point metal or the alloy.
Further, since the metal nitrides, the high melting point metals and the alloys of high melting point metals have a large electric resistivity, it has been impossible to perform electrolytic plating directly on a metal nitride, a high melting point metal or an alloy.
Therefore, in order to fill very small depressed portions with plating, it is necessary to form a seed layer to serve as a catalyst through electroless plating of copper, palladium or the like. A seed layer formed through a dry metallizing method is poor in providing uniform deposition onto the bottom portion and the side wall of a very small trench, which is an obstacle to making the wiring finer.
Accordingly, in regard to a method of forming the seed layer, a method which is excellent in uniform deposition capability for replacing the dry metallizing method is needed. Although there is a study concerning a substitution plating method using palladium for forming a seed layer, this method has a problem in the formation of finer wiring because palladium increases the resistivity of the wiring, as described above.
Although there is a study concerning a substitution plating method using copper, this method has a problem of poor adherence. Further, these substitution plating methods have a fatal problem in that sufficient reliability can not be secured because elution of the barrier layer occurs as the plating metal is deposited.